Compatible Boards
The following development boards are compatible with the M.2 M-key Stack FMC and can support at least one M.2 slot. If you know of a board that is not listed here and you would like to know if it is compatible, please contact us.
Note that we don’t currently have example designs for all of these carrier boards. For a list of carrier boards for which we do have example designs, please refer to the list of supported carriers in the reference design documentation.
Series-7 boards
| Carrier | FMC | Ref design | PCIe | M.2 Slot 1 | M.2 Slot 2 |
|---|---|---|---|---|---|
| AMD Xilinx KC705 Kintex-7 Development board | HPC | Yes | Gen2 | 4-lanes | Not supported |
| AMD Xilinx KC705 Kintex-7 Development board | LPC | Yes | Gen2 | 1-lane 1 | Not supported 1 |
| AMD Xilinx VC707 Virtex-7 Development board | HPC1 | Yes | Gen2 | 4-lanes | 4-lanes |
| AMD Xilinx VC707 Virtex-7 Development board | HPC2 | Yes | Gen2 | 4-lanes | 4-lanes |
| AMD Xilinx VC709 Virtex-7 Development board | HPC | Yes | Gen3 | 4-lanes | 4-lanes |
| AMD Xilinx ZC706 Zynq-7000 Development board | HPC | Yes | Gen2 | 4-lanes | Not supported 2 |
| AMD Xilinx ZC706 Zynq-7000 Development board | LPC | Yes | Gen2 | 1-lane 1 | Not supported 1 |
| Avnet PicoZed FMC Carrier Card V2 Zynq-7000 Development Board | LPC | Yes | Gen2 | 1-lane 1 | Not supported 1 |
UltraScale boards
| Carrier | FMC | Ref design | PCIe | M.2 Slot 1 | M.2 Slot 2 |
|---|---|---|---|---|---|
| AMD Xilinx KCU105 Kintex UltraScale Development board | HPC | Yes | Gen3 | 4-lanes | 4-lanes |
| AMD Xilinx KCU105 Kintex UltraScale Development board | LPC | Yes | Gen3 | 1-lane 1 | Not supported 1 |
| AMD Xilinx VCU108 Virtex UltraScale Development board | HPC0 | No | Gen3 | 4-lanes | 4-lanes |
| AMD Xilinx VCU108 Virtex UltraScale Development board | HPC1 | No | Gen3 | 4-lanes | 4-lanes |
Zynq Ultrascale+ boards
| Carrier | FMC | Ref design | PCIe | M.2 Slot 1 | M.2 Slot 2 |
|---|---|---|---|---|---|
| AMD Xilinx ZCU104 Zynq UltraScale+ Development board | LPC | Yes | Gen3 | 1-lane 1 | Not supported 1 |
| AMD Xilinx ZCU102 Zynq UltraScale+ Development board | HPC0 | No | Gen3 | 4-lanes 3 | 4-lanes 3 |
| AMD Xilinx ZCU102 Zynq UltraScale+ Development board | HPC1 | No | Gen3 | 4-lanes 3 | 4-lanes 3 |
| AMD Xilinx ZCU106 Zynq UltraScale+ Development board | HPC0 | Yes | Gen3 | 4-lanes | 4-lanes |
| AMD Xilinx ZCU106 Zynq UltraScale+ Development board | HPC1 | Yes | Gen3 | 1-lanes | Not supported |
| AMD Xilinx ZCU111 Zynq UltraScale+ Development board | FMC+ | Yes | Gen3 | 4-lanes | 4-lanes |
| AMD Xilinx ZCU208 Zynq UltraScale+ Development board | FMC+ | Yes | Gen3 | 4-lanes | 4-lanes |
| Avnet UltraZed EV Carrier Zynq UltraScale+ Development board | HPC | Yes | Gen3 | 4-lanes | 4-lanes |
| Trenz UltraITX+ Baseboard Zynq UltraScale+ Development board | HPC | No | Gen3 | 4-lanes 3 | 4-lanes 3 |
Ultrascale+ boards
| Carrier | FMC | Ref design | PCIe | M.2 Slot 1 | M.2 Slot 2 |
|---|---|---|---|---|---|
| AMD Xilinx VCU118 Virtex UltraScale+ Development board | HPC | No | Gen3 | Not supported | Not supported |
| AMD Xilinx VCU118 Virtex UltraScale+ Development board | FMC+ | No | Gen3 | 4-lanes | 4-lanes |
Versal boards
| Carrier | FMC | Ref design | PCIe | M.2 Slot 1 | M.2 Slot 2 |
|---|---|---|---|---|---|
| AMD Xilinx VCK190 Versal AI Core Development board | FMC+1 | No | Gen4 | 4-lanes | 4-lanes |
| AMD Xilinx VCK190 Versal AI Core Development board | FMC+2 | No | Gen4 | 4-lanes | 4-lanes |
| AMD Xilinx VMK180 Versal Prime Series Development board | FMC+1 | No | Gen4 | 4-lanes | 4-lanes |
| AMD Xilinx VMK180 Versal Prime Series Development board | FMC+2 | No | Gen4 | 4-lanes | 4-lanes |
| AMD Xilinx VPK120 Versal Premium Series Development board | FMC+ | No | Gen4 | 4-lanes | 4-lanes |
Compatibility requirements
If you need to determine the compatibility of a development board that is not listed here, or you are designing a carrier board to mate with the M.2 M-key Stack FMC, you can check your board against the list of requirements below.
Gigabit transceivers
The FPGA or MPSoC device must have gigabit transceivers and they must be routed to the FMC connector. For support of both M.2 slots, transceivers DP0-DP7 must all be connected to the FPGA. In the AMD Xilinx devices, the transceivers are typically grouped into quads containing 4 transceivers. Ideally, each M.2 slot should be connected to a single quad and the lane ordering should match the MGT ordering as shown in the tables below:
Quad 1
The first quad should be connected to M.2 slot 1 as follows:
| FPGA pin | PCIe lane | FMC Pin | FMC name | Net name |
|---|---|---|---|---|
| MGT_RXP/N0 | 0 | C6/C7 | DP0_M2C_P/N | SSDA2FPGA_0_P/N |
| MGT_TXP/N0 | 0 | C2/C3 | DP0_C2M_P/N | FPGA2SSDA_0_P/N |
| MGT_RXP/N1 | 1 | A2/A3 | DP1_M2C_P/N | SSDA2FPGA_1_P/N |
| MGT_TXP/N1 | 1 | A22/A23 | DP1_C2M_P/N | FPGA2SSDA_1_P/N |
| MGT_RXP/N2 | 2 | A6/A7 | DP2_M2C_P/N | SSDA2FPGA_2_P/N |
| MGT_TXP/N2 | 2 | A26/A27 | DP2_C2M_P/N | FPGA2SSDA_2_P/N |
| MGT_RXP/N3 | 3 | A10/A11 | DP3_M2C_P/N | SSDA2FPGA_3_P/N |
| MGT_TXP/N3 | 3 | A30/A31 | DP3_C2M_P/N | FPGA2SSDA_3_P/N |
The clock reference for this M.2 slot (FMC pins GBTCLK0_M2C_P/N) should be connected to MGTREFCLK0P/N or MGTREFCLK1P/N of this quad.
Quad 2
The second quad should be connected to M.2 slot 2 as follows:
| Direction | PCIe lane | FMC Pin | FMC name | Net name |
|---|---|---|---|---|
| MGT_RXP/N0 | 0 | A14/A15 | DP4_M2C_P/N | SSDB2FPGA_0_P/N |
| MGT_TXP/N0 | 0 | A34/A35 | DP4_C2M_P/N | FPGA2SSDB_0_P/N |
| MGT_RXP/N1 | 1 | A18/A19 | DP5_M2C_P/N | SSDB2FPGA_1_P/N |
| MGT_TXP/N1 | 1 | A38/A39 | DP5_C2M_P/N | FPGA2SSDB_1_P/N |
| MGT_RXP/N2 | 2 | B16/B17 | DP6_M2C_P/N | SSDB2FPGA_2_P/N |
| MGT_TXP/N2 | 2 | B36/B37 | DP6_C2M_P/N | FPGA2SSDB_2_P/N |
| MGT_RXP/N3 | 3 | B12/B13 | DP7_M2C_P/N | SSDB2FPGA_3_P/N |
| MGT_TXP/N3 | 3 | B32/B33 | DP7_C2M_P/N | FPGA2SSDB_3_P/N |
The clock reference for this M.2 slot (FMC pins GBTCLK1_M2C_P/N) should be connected to MGTREFCLK0P/N or MGTREFCLK1P/N of this quad.