The example designs for the FPGA Drive FMC Gen4 are released open source under the MIT license and maintained on Github. We strongly encourage community contributions to the example designs.
|FPGA Drive FMC Example Design||More info||Git repo||Docs|
FPGA Drive FMC example design
This example design demonstrates use of one or two SSDs with the carrier boards listed below. The main IP in the design implements the PCIe root complex. The design can be used with a baremetal application that reports on the status of the PCIe links and performs enumeration of the detected SSDs. The design also can be used with a custom PetaLinux build that allows the SSDs to be accessed through standard Linux commands and a file system.
Supported carrier boards
The Git repo contains an example design for each of the following carrier boards.
- AMD Xilinx KC705 Kintex-7 Development board
- AMD Xilinx VC707 Virtex-7 Development board
- AMD Xilinx VC709 Virtex-7 Development board
- AMD Xilinx ZC706 Zynq-7000 Development board
- Avnet PicoZed FMC Carrier Card V2 Zynq-7000 Development Board
- AMD Xilinx KCU105 Kintex UltraScale Development board
- AMD Xilinx ZCU104 Zynq UltraScale+ Development board
- AMD Xilinx ZCU106 Zynq UltraScale+ Development board
- AMD Xilinx ZCU111 Zynq UltraScale+ Development board
- Avnet UltraZed EV Carrier Zynq UltraScale+ Development board
Some of these boards have more than one FMC connector that can support FPGA Drive FMC Gen4, while some of them have specific limitations on the number of SSDs or PCIe lanes that they can support. For more information about these limitations, refer to the reference design documentation.
The reference design documentation provides a list of tested SSDs to help guide your selection of SSD for use with FPGA Drive FMC Gen4.